Show HN: AirFlick Drop – AirDrop for Windows with zero mobile app installs https://ift.tt/YUkq93n

Show HN: AirFlick Drop – AirDrop for Windows with zero mobile app installs https://ift.tt/th2p7D3 November 2, 2026 at 02:08AM

Show HN: Jik – a self-hosted language using region-based memory management https://ift.tt/kN38VgP

Show HN: Jik – a self-hosted language using region-based memory management https://ift.tt/iSP6na4 November 2, 2026 at 01:21AM

Show HN: Offline project memory for coding agents – no API key, no vector DB https://ift.tt/d3tmHZL

Show HN: Offline project memory for coding agents – no API key, no vector DB https://ift.tt/MzoYics November 1, 2026 at 11:27PM

Show HN: InterviewLint – Practice explaining code, not just writing it https://ift.tt/YiVcHPA

Show HN: InterviewLint – Practice explaining code, not just writing it https://ift.tt/VvG3WYK October 31, 2026 at 11:36PM

Show HN: A language model that lives in a boot sector https://ift.tt/2jgz1K0

Show HN: A language model that lives in a boot sector All the ideas came from the boot sector demo scene where people had been writing chess and BASIC games in 512 bytes, even a C compiler. I wondered what one can do using a neural network instead of a program and generating boot logs for non-existent hardware was something fun to try. Entire inference engine is 510 bytes of MBR, weights, vocab, and strings reside in the sectors following MBR. Small char-level neural network was trained on dmesg generated by machine, so machine produces Linux boot messages infinitely. train.py performs precisely the same integer arithmetic operations as the asm code does and thus produces an output identical character-by-character to the one produced by QEMU. The difference analysis revealed my favorite bug. The characters at the beginning matched those generated by the simulator, but then the output diverged. I retrieved the hidden layer via QEMU’s debug port and compared the neurons' values with those of the simulator, one neuron at a time. Only the value of the first neuron was correct. The activation involves idiv, and idiv stores its remainder in edx. The pointer to the biases table was stored in edx, which resulted in the first neuron being biased correctly and the following ones using garbage. Now the bias' address is determined from the loop counter, and no pointers have to survive the division. Another bug I found simply by looking at the code before I did my first run-through: the BIOS print routine zeros out bx, but bx contains the predicted character number. This explains the push and pop of bx surrounding the print. sectorllm is the most similar to my project, as it runs an actual 5-layer llama2 with attention mechanism in just 1.2K of assembly code. It is the trade-off in the opposite direction, as my engine needs to fit into one sector and therefore my network has just one hidden layer of int8 operations for dreaming the dmesg. https://ift.tt/v061t8S October 31, 2026 at 06:28PM

Show HN: I rebuilt Kubernetes for ESP32 microcontrollers https://ift.tt/iqlA3fp

Show HN: I rebuilt Kubernetes for ESP32 microcontrollers https://ift.tt/CbQAIUG October 29, 2026 at 10:05PM

Show HN: SLCR – An open standard for agent-native software requirements https://ift.tt/zD1n46R

Show HN: SLCR – An open standard for agent-native software requirements https://slcr.dev/ October 29, 2026 at 10:13PM